Method of manufacturing SOI element having body contact

ABSTRACT

A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a continuation of co-pending U.S.patent application Ser. No. 09/032,214, filed on Feb. 27, 1998, priorityof which is hereby claimed under 35 U.S.C. § 120. The presentapplication also claims priority under 35 U.S.C. § 119 and Rule 55 toJapanese patent Application No. 9-046688, filed on Feb. 28, 1997. All ofthese applications are expressly incorporated herein by reference asthough fully set forth in full.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor device and amethod of manufacturing the same and, more particularly, a SOI (SiliconOn Insulator) type semiconductor device and a method of manufacturingthe same.

[0003] As the reduction in power consumption of semiconductor integratedcircuits and the enhancement in mounting density thereof are furthered,the miniaturization of the individual elements constituting theintegrated circuits and the lowering in operating voltages thereof arestrongly desired. In the case of a conventional bulk planar typeelements, as a result of the miniaturization of the elements and thereduction in channel length thereof, a short-channel effect isactualized; and, in order to prevent it, technical measures such as theenhancement of the impurity density in the substrate, the thinning ofthe gate insulator, etc. have been taken in accordance with severalelement size-reduction rules. However, as a matter of fact, as theelements are further and further miniaturized, the existence of somephysical limits is encountered; and thus, in order to achieve a furtherminiaturization, some novel element structures have come to be proposed.As one such novel element structure, there can be pointed out a SOIelement which has an insulator under an active region thereof.

[0004] Next, typical examples of the structure of an SOI element and themethod of the manufacturing the same will be described below. First,FIG. 1 shows a sectional view taken along the direction of the channellength of the SOI element. On a monocrystalline silicon (Si)semiconductor substrate 1, a monocrystalline silicon (Si) active layer 3is formed through, e.g. a silicon oxide layer (SiO₂) 2, and further, agate electrode 9 is formed through, e.g. a silicon oxide layer (SiO₂) 8which is to be used as a gate insulator. Further, a source region 4-1and a drain region 4-2 are formed by introducing, by the use of ionimplantation method, an impurity of the conductivity type opposite tothat of a silicon active layer 4-3 which is to be used as a channelregion.

[0005] However, the SOI element which has thus been formed isadvantageous, in view of improving the element characteristics thereof,in that the film thickness of the active layer can be reduced, but onthe other hand, due to the fact that the source and drain diffusionlayers or the depletion layer extending from the source and draindiffusion layers reach even the insulator lying under the active layer,it is it is structurally difficult to control the potential in the bodyregion so easily as in the case of a conventional bulk planar typeelement. As a result, there takes place the phenomenon that thepotential in the body region floats during the operation of the element,thus posing problems such as the problem that, during the operation ofthe element, the threshold voltage of the element changes.

[0006] As countermeasures to these problems, attempts have been made tocontrol the potential in the channel region of the thin-film SOIelement.

[0007] For instance, in Japanese Patent Publication (KOKAI) No.61-34978, it is proposed to form an electrode, between the isolationregion and the buried insulator thereunder, for providing a potential tothe channel region from outside. According to this method, however, theisolation insulator is formed in such a manner that the isolation regionis previously oxidized into a thin film by selectively controlling theamount thereof, and further, the thicknesses of the contact portion tothe channel region and the isolation region are controlledsimultaneously and repeatedly again to form the isolation dielectric.Thus, the method has the problem or defect that it is very difficult tocontrol the amount of the SOI layer at the respective manufacturingsteps for the reduction in thickness of the SOI layer intended in viewof improving the performances, and at the same time, the increase in thenecessary area occupied by the element is increased.

[0008] As described above, mainly in the case of a conventionalthin-film SOI element, there are problems or defects such as the defectthat the manufacturing steps thereof become complicated as compared withthe formation of a conventional bulk planar type element, and further,the area occupied by the element is substantially increased.

BRIEF SUMMARY OF THE INVENTION

[0009] It is the object of the present invention to provide, mainly, aSOI type semiconductor device and a method of manufacturing thesemiconductor device, according to which the miniaturization of thesemiconductor device, the enhancement in operating speed thereof, andthe reduction in power consumption thereof can be realized.

[0010] To achieve the above subject, according to the present invention,the following means are employed.

[0011] The main point of the present invention lies in that, in the stepof forming the isolation region, the isolation width thereof and theformation condition thereof are varied, whereby, in a desired area, aregion in which an isolation layer formed from the surface of a channellayer does not extend as far as an insulator positioned under an activelayer which lies under the isolation layer is formed in a self-aligningmanner, and, through the region, a region for controlling the potentialin a body region is formed.

[0012] The semiconductor device according to the present inventioncomprises a semiconductor substrate having a first insulator, and asemiconductor channel region formed on the first insulator, wherein thesemiconductor channel region comprising at least two first regions bothhaving the first conductivity type, a second region of the conductivitytype opposite to the first conductivity type, the second region beingprovided between the two first regions, a second insulator formed on thesecond region, a gate electrode formed on the second insulator, a thirdregion having the same conductivity type as that of the second region,the third region being electrically conductive to the second region, athird insulator formed on the third region, the third insulator having awidth narrower than the widths of an isolation region for isolating thesemiconductor formation region, and a fourth region of the sameconductivity type as that of the third region, the fourth region beingelectrically conductive to the third region. In connection with this, itis preferable that the gate electrode is formed on the second region andthe fourth region. Further, it is effective that the gate electrode iselectrically conductive to the fourth region, and the gate electrode isformed on the fourth region through a fourth insulator.

[0013] The above-mentioned method of manufacturing a semiconductordevice according to the present invention comprises the step of formingthe third insulator simultaneously with the formation of the isolationregion by making the interval between the second region and the fourthregion narrower than the width of the isolation region at the time offorming the isolation region so as to extend as far as the firstinsulator in order to isolate the semiconductor channel region.

[0014] Further, the method of manufacturing a semiconductor device,which comprises a semiconductor substrate having a first insulator and asemiconductor channel region formed on the first insulator, thesemiconductor channel region including at least two first regions of afirst conductivity type, a second region provided between the firstregions and having the conductivity type opposite to the firstconductivity type, a second insulator formed on the second region, agate electrode formed on the second insulator, a third region having thesame conductivity type as that of the second region and beingelectrically conductive to the second region, a third insulator formedon the third region, and a fourth region having the same conductivitytype as that of the third region and being electrically conductive tothe third region, according to the present invention comprises the stepof forming the third insulator simultaneously with the formation of theisolation region by narrowing the interval between the second region andthe fourth region than the width of the isolation region at the time offorming the isolation region so as to extend as far as the firstinsulator in order to isolate the semiconductor channel region. Inconnection with this, it is preferable that the gate electrode is formedon the second region and the fourth region. Further, it is effectivethat the gate electrode is electrically conductive to the fourth region,and the gate electrode is formed on the fourth region through a fourthinsulator

[0015] By using the above-mentioned method, the electrode forcontrolling the potential in the body region can be formed withoutcomplicating the manufacturing steps as compared with the conventionalbulk planar type element and by suppressing the increase of the arearequired. As a result, the problem pertaining to the floating effect ofthe body potential can be eliminated, and further, the body potentialsof the individual elements can be arbitrarily controlled, so that acircuit operation etc. which could not be realized through theconventional bulk planar type elements can be achieved.

[0016] As mentioned above, according to the present invention, it ismade possible, by controlling the width and film thickness of theisolation region, to form a thin-film SOI element in which the bodypotential can be controlled without increasing the number ofmanufacturing steps, complicating the structure of the element orincreasing the area occupied by the element.

[0017] Additional objects and advantages of the present invention willbe set forth in the description which follows, and in part will beobvious from the description, or may be learned by practice of thepresent invention. The objects and advantages of the present inventionmay be realized and obtained by means of the instrumentalities andcombinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the present invention and, together with the generaldescription given above and the detailed description of the preferredembodiments given below, serve to explain the principles of the presentinvention in which:

[0019]FIG. 1 is a sectional view showing a conventional semiconductordevice;

[0020]FIG. 2 is a sectional view of the semiconductor device, after thefirst manufacturing step, according to a first embodiment of the presentinvention;

[0021]FIGS. 3A and 3B are respectively a plan view and a sectional viewtaken along the line 3B-3B in FIG. 3A of the semiconductor device afterthe second manufacturing step according to the first embodiment of thepresent invention;

[0022]FIG. 4 is a sectional view of the semiconductor device after thethird manufacturing step according to the first embodiment of thepresent invention;

[0023]FIGS. 5A and 5B are respectively a plan view and a sectional viewtaken along the line 5B-5B in FIG. 5A, of the semiconductor device afterthe fourth manufacturing step of the first embodiment of the presentinvention;

[0024]FIG. 6 is a sectional view of the semiconductor device accordingto the first embodiment of the present invention;

[0025]FIG. 7 is a sectional view of the semiconductor device accordingto a second embodiment of the present invention;

[0026]FIG. 8 is a graph showing the characteristic of the semiconductordevice according to the second embodiment of the present invention; and

[0027]FIGS. 9A and 9B are respectively a plan view and a sectional viewtaken along the line 9B-9B in FIG. 9A, of the semiconductor deviceaccording to a third embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] The present invention will now be described referring to thedrawings.

[0029] FIGS. 2 to 6 are schematic diagrams showing the manufacturingsteps for explaining the first embodiment of the method of manufacturinga semiconductor device according to the present invention.

[0030] First, as shown in FIG. 2, a SOI layer 3 formed through, e.g. anoxide layer 2 on a semiconductor substrate 1 by means of SIMOX or waferbonding is thinned into a layer having a desired thickness of, e.g.about 150 nm by the use of the thermal oxidation method and an etchingmethod using NH₄F.

[0031] Next, as shown in FIGS. 3A and 3B, an isolation region 6 isformed in a desired area in order to separate the SOI layer 3 into anchannel region 4 and a body contact region 5. In this case, theisolation width L between the channel region 4 and the body contactregion 5 is arranged so as to become narrower than the other isolationwidths. By selecting this isolation width L so as to be narrower thanthe other isolation widths, it is ensured that, even in case theisolation region is formed at the same time as according to the presentinvention, the portion of the isolation region lying between the channelregion 4 and the body contact region 5 is not oxidized as far as theoxide layer 2 unlike in the case of the other portions of the isolationregion. The isolation width L is determined by means of, e.g.simulation. The isolation region is formed by the use of, e.g. the LOCOSmethod, in which case the insulator, which is rendered into theisolation region is formed by oxidizing mainly the SOI layer. In thiscase, the amount of oxidation of the SOI layer is controlled, whereby,in the wider portion of the isolation region, the whole SOI layer isoxidized.

[0032] Here, it should be noted that, in the case of the portion of theisolation region which lies between the channel region 4 and the bodycontact reason 5 and has the isolation width L narrower than the widthsof the other portions of the isolation region, it never happens that thewhole SOI region is oxidized as far as the oxide layer 2, so that, asshown in FIG. 4, a region 7 connecting the channel region 4 and the bodycontact region 5 to each other can be formed beneath the elementisolation insulating film.

[0033] Next, desired impurities are injected into the channel region 4,the body contact region 5 and the region 7 which connects them togetherby the use of the ion implantation method, and thereafter, as shown inFIGS. 5A and 5B, a gate electrode 9 is formed through a gate insulator 8on the isolation region 6 and the SOI layer 3 excepting the body contactregion 5.

[0034] Next, the body contact region 5 is masked by the use of, e.g. aresist (not shown), a desired impurity is introduced for the formationof the source and drain regions 4-1 and 4-2 of the element. After this,an annealing treatment is carried out using a thermal step such as, e.g.the RTA (Rapid Thermal Annealing) method for activation of the impurityintroduced by the use of the ion implantation method.

[0035] Thereafter, the step of forming a wiring for providing contacts11 and 12 (the source contact and the drain contact being not shown)respectively to the source and drain regions 4-1 and 4-2, the gateelectrode 9, and the body contact region 5 through an interleveldielectric 10 is performed, whereby a desired SOI type semiconductordevice shown in FIG. 6 is completed.

[0036] In the case of the thin-film SOI element formed in accordancewith the first embodiment of the present invention, the abnormaloperation due to float the potential in the body region can besuppressed by controlling the body potential in spite of the fact thatthe method of manufacturing the SOI element is approximately the same asthe conventional method.

[0037] Further, in the case of the element according to the presentinvention, when the element operates, the channel inversion layerthrough which the current flowing between the source and drain passesand the body potential contact region can be isolated from each other bythe isolation region, so that, between the source, the drain and thechannel inversion layer and the body potential control contact, nohigh-density pn-junction is formed, so that the leakage current from thebody contact region can be structurally reduced.

[0038]FIG. 7 is a schematic diagram showing a second embodiment of thesemiconductor device according to the present invention, wherein thesame portions as those shown in the drawings pertaining to the firstembodiment shown are denoted by the same reference numerals, whereby therepetition of the description thereof is omitted.

[0039] The above-described first embodiment is of the structureconstructed in such a manner that the channel potential is given fromoutside, but even if the thin-film SOI element is formed, for instance,in such a manner that, after the element isolation 6 is formed and then,on the channel region 4 and the body contact region 5, the gateinsulator (not shown) is formed, and thereafter, the insulator on thebody contact region 5 is selectively removed to form the gate electrodeas shown in FIG. 7, it is also possible to control the potential of thebody contact region 5 like the gate potential.

[0040] In case the above-mentioned structure is employed, a very goodcut-off characteristic is exhibited as shown in FIG. 8 due to thesubstrate bias effect of the element in case, particularly, theoperating voltage range is below the built-in potential induced at thepn-junction between the source and drain diffusion layer and the bodyregion. Thus, according to the second embodiment of the presentinvention, a semiconductor device having a very good cut-offcharacteristic can be realized without being followed by an increase ofunnecessary leakage current and without increasing the manufacturingsteps and the area occupied by the element.

[0041]FIGS. 9A and 9B are schematic diagrams showing a third embodimentof the semiconductor device according to the present invention. In thesedrawings, the same portions as those shown in the drawings pertaining tothe first embodiment are denoted by the same reference numerals, wherebythe repetition of the description thereof is omitted.

[0042] The semiconductor device shown in FIGS. 9A and 9B is constructedin such a manner that, with the formation, between the contact regionfor controlling the body potential and the gate electrode 9 formed offor instance a polycrystalline semiconductor, of an insulator similar tothat of the channel region, the portion of the gate electrode 9 lying onthe body contact region 5 is rendered into the conductivity type same asthat of the body contact region. Portion of the gate electrode 9 lyingon the channel region 4, and further, a material such as for instancetungsten polycide or the like is provided in such a manner as to extendover the portions of the polycrystalline semiconductor gate electrode 9lying on the body contact region 5 and the channel region 4,respectively, to thereby make the portions electrically conductive toeach other. By adopting such a structure, it is ensured that, in casethe gate voltage is transiently applied in operating the semiconductordevice, the body potential can be changed, as in the case of the secondembodiment, by the capacitive coupling formed in the body contact region5. In particular, this third embodiment has the advantage that, in thecircuit operating at high frequency, preventing the leakage current fromthe electrode which provides a body potential, the body bias effect dueto capacitive coupling can be effectively utilized.

[0043] The present invention is not limited only to the foregoingembodiments. According to the present invention, for instance as themonocrystalline layer formed on the insulator, not only the SOIsubstrate formed by the use of the above-mentioned SIMOX method or thewafer bonding method, but also a monocrystalline layer stuck on aninsulation substrate and an SOS (Silicon On Sapphire) can be used.

[0044] It is a matter of course that the present invention can bevariously modified within the technical scope of the present invention.

[0045] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the present invention in itsbroader aspects is not limited to the specific details, representativedevices, and illustrated examples shown and described herein.Accordingly, various modifications may be made without departing fromthe spirit or scope of the general inventive concept as defined by theappended claims and their equivalents.

1. A method of manufacturing a semiconductor device, which comprises: asemiconductor substrate having a first insulator and a semiconductorlayer formed on said first insulator, said semiconductor layer includinga plurality of active regions each including at least two source-drainregions of a first conductivity type, a channel region provided betweensaid source-drain regions and having a second conductivity type oppositeto said first conductivity type, a gate insulator formed on said channelregion, a gate electrode formed on said gate insulator, a channel-bodycontact connection region having the same conductivity type as that ofsaid channel region and being electrically conductive to said channelregion, a second insulator formed on said channel-body contactconnection region, and a body contact region having the sameconductivity type as that of said channel-body contact connection regionand being electrically conductive to said channel-body contactconnection region, and an isolation region which electrically isolatessaid plurality of active regions, said method comprising the step of:forming said second insulator simultaneously with the formation of anisolation region without varying thickness of said semiconductor layer,whereby a distance between said channel region and said body contactregion is narrower than the width of said isolation region at the timeof forming said isolation region, said isolation region formed so as toextend as far as said first insulator in order to isolate saidsemiconductor layer.
 2. A method of manufacturing the semiconductordevice according to claim 1, wherein said gate electrode is formed onsaid channel region and said body contact region.
 3. A method ofmanufacturing the semiconductor device according to claim 2, whereinsaid gate electrode is electrically conductive to said body contactregion.
 4. A method of manufacturing the semiconductor device accordingto claim 2, wherein said gate electrode is formed on said body contactregion through a body contact insulator.
 5. A method of manufacturing asemiconductor device comprising: preparing a semiconductor substrate;forming an oxide film on said semiconductor substrate; forming an activelayer on said oxide film; and forming an isolation region in a desiredregion of said active layer to separate said active layer into a channelregion and a body contact region, an isolation width between saidchannel region and said body contact region being narrower than theother isolation widths.
 6. The method according to claim 5, wherein saidisolation is formed by LOCOS method.
 7. The method according to claim 5,wherein the isolation width is calculated by a simulation.
 8. The methodaccording to claim 5, wherein said forming an isolation region includesforming a region which connects said channel region and said bodycontact region.
 9. The method according to claim 5, further comprisingforming a gate electrode on said channel region.